/**
  ******************************************************************************
  * @file    Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h 
  * @author  MCD Application Team
  * @version V3.5.0
  * @date    08-April-2011
  * @brief   This file contains the headers of the interrupt handlers.
  ******************************************************************************
  * @attention
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  ******************************************************************************
  */ 

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_IT_H
#define __STM32F10x_IT_H

#ifdef __cplusplus
 extern "C" {
#endif 

/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"

/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */

void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void USART2_IRQHandler(void);
void USART1_IRQHandler(void);
	void TIM2_IRQHandler(void);
	
	void TIM3_IRQHandler(void);
	//void ADC1_IRQHandler(void);
#if 0
	/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
	  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
	  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
	  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
	  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
	  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
	  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
	  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
	  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */

	/******  STM32 specific Interrupt Numbers *********************************************************/
	  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
	  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
	  TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
	  RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
	  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
	  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
	  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
	  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
	  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
	  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
	  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
	  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
	  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
	  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
	  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
	  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
	  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
	  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */

		ADC1_IRQn 									= 18, 		/*!< ADC1 global Interrupt																*/
		EXTI9_5_IRQn								= 23, 		/*!< External Line[9:5] Interrupts												*/
		TIM1_BRK_TIM15_IRQn 				= 24, 		/*!< TIM1 Break and TIM15 Interrupts											*/
		TIM1_UP_TIM16_IRQn					= 25, 		/*!< TIM1 Update and TIM16 Interrupts 										*/
		TIM1_TRG_COM_TIM17_IRQn 		= 26, 		/*!< TIM1 Trigger and Commutation and TIM17 Interrupt 		*/
		TIM1_CC_IRQn								= 27, 		/*!< TIM1 Capture Compare Interrupt 											*/
		TIM2_IRQn 									= 28, 		/*!< TIM2 global Interrupt																*/
		TIM3_IRQn 									= 29, 		/*!< TIM3 global Interrupt																*/
		TIM4_IRQn 									= 30, 		/*!< TIM4 global Interrupt																*/
		I2C1_EV_IRQn								= 31, 		/*!< I2C1 Event Interrupt 																*/
		I2C1_ER_IRQn								= 32, 		/*!< I2C1 Error Interrupt 																*/
		I2C2_EV_IRQn								= 33, 		/*!< I2C2 Event Interrupt 																*/
		I2C2_ER_IRQn								= 34, 		/*!< I2C2 Error Interrupt 																*/
		SPI1_IRQn 									= 35, 		/*!< SPI1 global Interrupt																*/
		SPI2_IRQn 									= 36, 		/*!< SPI2 global Interrupt																*/
		USART1_IRQn 								= 37, 		/*!< USART1 global Interrupt															*/
		USART2_IRQn 								= 38, 		/*!< USART2 global Interrupt															*/
		USART3_IRQn 								= 39, 		/*!< USART3 global Interrupt															*/
		EXTI15_10_IRQn							= 40, 		/*!< External Line[15:10] Interrupts											*/
		RTCAlarm_IRQn 							= 41, 		/*!< RTC Alarm through EXTI Line Interrupt								*/
		CEC_IRQn										= 42, 		/*!< HDMI-CEC Interrupt 																	*/
		TIM12_IRQn									= 43, 		/*!< TIM12 global Interrupt 															*/
		TIM13_IRQn									= 44, 		/*!< TIM13 global Interrupt 															*/
		TIM14_IRQn									= 45, 		/*!< TIM14 global Interrupt 															*/
		TIM5_IRQn 									= 50, 		/*!< TIM5 global Interrupt																*/
		SPI3_IRQn 									= 51, 		/*!< SPI3 global Interrupt																*/
		UART4_IRQn									= 52, 		/*!< UART4 global Interrupt 															*/
		UART5_IRQn									= 53, 		/*!< UART5 global Interrupt 															*/	
		TIM6_DAC_IRQn 							= 54, 		/*!< TIM6 and DAC underrun Interrupt											*/
		TIM7_IRQn 									= 55, 		/*!< TIM7 Interrupt 																			*/	
		DMA2_Channel1_IRQn					= 56, 		/*!< DMA2 Channel 1 global Interrupt											*/
		DMA2_Channel2_IRQn					= 57, 		/*!< DMA2 Channel 2 global Interrupt											*/
		DMA2_Channel3_IRQn					= 58, 		/*!< DMA2 Channel 3 global Interrupt											*/
		DMA2_Channel4_5_IRQn				= 59, 		/*!< DMA2 Channel 4 and Channel 5 global Interrupt				*/
		DMA2_Channel5_IRQn					= 60			/*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is 
																							 mapped at position 60 only if the MISC_REMAP bit in 
																							 the AFIO_MAPR2 register is set)											*/			 
#endif

	

#ifdef __cplusplus
}
#endif

#endif /* __STM32F10x_IT_H */

/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
